Two-Level Address Storage and Address Prediction

The amount of information recorded in the prediction tables of the proposed address predictors turns out to be comparable to the current on-chip cache sizes; for instance, a last-address predictor that records 4.096 64-bit effective addresses uses a 32 Kbytes storage space. Area cost of address predictors is proportional to address width. To reduce their area cost, we will take advantage of the spatial-locality property of the memory references, that is, the high-order bits of several effective addresses recorded in the prediction table are equal. Then, the effective addresses are split in two parts: the high-order bits and the low-order bits. The High-Address Table records the high-order bits and the Low-Address Table records the low-order bits and a link between tables. This organization allows addresses with the same high-order bits to share one entry in the High-Address Table. We use this organization in a last-address predictor and our evaluations show that it produces significant area-cost reductions (28%-60%) without performance losses. Keywordsaddress prediction, address locality, area cost